Tony wrote:

Providing that there's a way to get a bunch of cheapo CPUs to do the job.

True, but there's a complexity hit (which translates into a reliability hit and a development lag) from this approach.

Well, i do not think that using off-the-shelf cheapo CPUs debugged by somebody else and tested in millions of applications, instead of single-purpose ASICs qualifies as a reliability hit or a development lag :) --vadim