Tony Li wrote:
So the problem is that as we approach higher speed (post-7500) interfaces, you're forced into more specialized hardware. At this point, not having an SSE ASIC becomes somewhat silly. The rest of the board is ASICs, which in volume end up cheaper than processors...
There's not enough volume in high-end box market to get to the break-even point on the price-performance. Providing that there's a way to get a bunch of cheapo CPUs to do the job. And don't forget the DRAM vs SRAM issue. I did the arithmetic. --vadim
There's not enough volume in high-end box market to get to the break-even point on the price-performance. That's not clear. Providing that there's a way to get a bunch of cheapo CPUs to do the job. True, but there's a complexity hit (which translates into a reliability hit and a development lag) from this approach. And don't forget the DRAM vs SRAM issue. I did the arithmetic. Fortunately, there are new memory technologies today that are more interesting than those when we started work on the SSE. And ASIC technology helps you further here... Tony
participants (2)
-
Tony Li -
Vadim Antonov