can the memory technology save the routing table size scalability problem?
As we known, the DFZ RIB size expand rapidly. It may be resolved via router architecture improvement, such as adding memory chips or compressing RIB. or via changing routing and addressing scheme, which one will be the long-term essential approach?
You could try this recent nanog thread for some ideas Route table growth and hardware limits...talk to the filter http://www.merit.edu/mail.archives/nanog/msg02822.html srs On Jan 9, 2008 7:55 AM, yangyang. wang <wyystar@gmail.com> wrote:
As we known, the DFZ RIB size expand rapidly. It may be resolved via router architecture improvement, such as adding memory chips or compressing RIB. or via changing routing and addressing scheme, which one will be the long-term essential approach?
-- Suresh Ramasubramanian (ops.lists@gmail.com)
On Jan 8, 2008 9:25 PM, yangyang. wang <wyystar@gmail.com> wrote:
As we known, the DFZ RIB size expand rapidly. It may be resolved via router architecture improvement, such as adding memory chips or compressing RIB. or via changing routing and addressing scheme, which one will be the long-term essential approach?
There are at least 2 problems to be addressed (given that you believe 'too many routes will crush the dfz routers')... both number of routes and speed/number of updates. So, adding more MEMORY (pick your type DRAM/SRAM/bah) is only solving one of the problems. Additionally, most moderm DFZ-placed platforms aren't necessarily 'RAM' limited, some of the limits exist in hardware forwarding elements (TCAM/CAM/ASIC systems). Anyway, Suresh's followup has a decent info as well, you might locate the RRG and RAM/RAWs working group meeting outputs as well: (report) http://tools.ietf.org/html/rfc4984 -Chris
participants (3)
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Christopher Morrow -
Suresh Ramasubramanian -
yangyang. wang