I'm less assuming it and more reading it from this SIGCOMM paper: https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf
Which doesn't cover the subject at hand. Owen is correct here. The LU block has separate reduced latency RAM that holds the data it uses. (The FIB). Other memory in the chip is used for the other non-lookup functions. On Fri, Sep 29, 2023 at 6:14 PM William Herrin <bill@herrin.us> wrote:
On Fri, Sep 29, 2023 at 3:11 PM Owen DeLong <owen@delong.com> wrote:
You continue to assume that there is a fast SRAM cache. I’m not sure that is true. I think that all of the FIB RAM on the line cards is fast SRAM and no cache.
Hi Owen,
I'm less assuming it and more reading it from this SIGCOMM paper: https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf
Regards, Bill Herrin
-- William Herrin bill@herrin.us https://bill.herrin.us/