DPDK doesn't inherently do much in the way of power management.
I agree - it doesn't. That's not what it was made for.

 Note that DPDK applications are usually intended to run in very-high
data rate environments where no gains are likely to be realized by
avoiding a busy-wait loop.

That's not what research shows. 

Use of LPI states is proposed for power management under high data rate conditions in [5] and 
in [6], use of the low-power instruction halt  is investigated and found to save power under such conditions.

Cheers,

Etienne

[3] X. Li, W. Cheng, T. Zhang, F. Ren, and B. Yang, “Towards Power Efficient High Performance Packet I/O,” 
IEEE Transactions on Parallel and Distributed Systems, vol. 31, no. 4, pp. 981–996, April 2020, 
ISSN:1558-2183. DOI: 10.1109/TPDS.2019.2957746

[5] R. Bolla, R. Bruschi, F. Davoli, and J. F. Pajo, “A Model-Based Approach Towards Real-Time Analytics in NFV Infrastructures,” 
IEEE Transactions on Green Communications and Networking, vol. 4, no. 2, pp. 529–541, Jun. 2020, ISSN: 2473-2400. 
DOI: 10.1109/TGCN.2019.2961192.


On Tue, Feb 23, 2021 at 11:04 PM William Herrin <bill@herrin.us> wrote:
On Mon, Feb 22, 2021 at 11:24 PM Etienne-Victor Depasquale
<edepa@ieee.org> wrote:
>>
>> Beyond RX/TX CPU affinity, in DANOS you can further tune power consumption by changing the adaptive polling rate.  It doesn’t, per the survey, "keep utilization at 100% regardless of packet activity.”
>
> Robert, you seem to be conflating DPDK
> with DANOS' power control algorithms that modulate DPDK's default behaviour.
> Keep in mind that this is a bare-bones survey intended for busy, knowledgeable people (the ones you'd find on NANOG) -

Hi,

Since you understand that, I'm not really clear what you're asking in
the survey.

DPDK doesn't inherently do much in the way of power management. The
polling loops are in the application side of the software, not the
DPDK libraries or NIC driver. It's up to the application author to
decide to detect idleness in the polling loop and take action to
reduce CPU load. If they go for a simple busy-wait, the dataplane
cores run at 100% all the time regardless of packet load. This has the
expected impact on the server's power consumption.

Note that DPDK applications are usually intended to run in very-high
data rate environments where no gains are likely to be realized by
avoiding a busy-wait loop.

Regards,
Bill Herrin


--
William Herrin
bill@herrin.us
https://bill.herrin.us/


--
Ing. Etienne-Victor Depasquale
Assistant Lecturer
Department of Communications & Computer Engineering
Faculty of Information & Communication Technology
University of Malta
Web. https://www.um.edu.mt/profile/etiennedepasquale