On Fri, Sep 29, 2023 at 3:26 PM Owen DeLong <owen@delong.com> wrote:
On Sep 29, 2023, at 15:14, William Herrin <bill@herrin.us> wrote: I'm less assuming it and more reading it from this SIGCOMM paper: https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf
Fair enough, but interestingly, I think that the compiled line-card forwarding table probably always fits in the cache.
If I were designing the product, I'd size the SRAM with that in mind. I'd also keep two full copies of the FIB in the outer DRAM so that the PPEs could locklessly access the active one while the standby one gets updated with changes from the RIB. But I'd design the router to gracefully fail if the FIB exceeded what the SRAM could hold. When a TCAM fills, the shortest prefixes are ejected to the router's main CPU. That fails pretty hard since the shortest prefixes tend to be among the most commonly used. By comparison, an SRAM cache tends to retain the most commonly used prefixes as an inherent part of how caches work, regardless of prefix length. It can operate close to full speed until the actively used routes no longer fit in the cache. Regards, Bill Herrin -- William Herrin bill@herrin.us https://bill.herrin.us/