Our softswitch vendor talks about control plane bandwidths for geo-redundant configurations on the low end of your numbers. I'd have to drag out the slide deck to see exactly what they recommended. My point is that carrier-class products have demonstrated it's possible. Frank From: Tim Jackson [mailto:jackson.tim@gmail.com] Sent: Monday, November 12, 2012 9:36 AM To: Kasper Adel Cc: Frank Bulk; NANOG list Subject: Re: Whats so difficult about ISSU I would argue no. The Class 5 softswitches that are around now are off-the-shelf cPCI or ACTA hardware running Linux or some other *nix. The TDM -> IP cards are the only sticky point there to be upgraded, but since everything is a mid-plane, you can do rolling N:1 upgrades across the cards with minimal (sub 400msec) impact. There's not a ton special secret sauce there.. To the other point, they probably process way more than 2mbps/s of control traffic during busy hour, especially in geo-redundant configurations as lots of things have to be synchronized. I think you're talking more on the order of 50-120mbps.. Yet all of this works pretty damn well. -- Tim On Mon, Nov 12, 2012 at 12:21 AM, Kasper Adel <karim.adel@gmail.com> wrote: Hi Frank, Is it because C5 softswitches have expensive hardware, advanced software and dual asics? I would have never imagined that any vendor is capable of upgrading fpd's/ASICs ucode without a hit unless there are multiple chips continuously syncing with each other. Regards, Kim On Monday, November 12, 2012, Frank Bulk wrote:
We do it on our Class 5 softswitch ... and it works consistently. There may be a few seconds, once, where a new call can't be made, but most people will re-dial. It just works.
It can be done, but the product has to be built with that in mind.
Frank
-----Original Message-----
From: Kasper Adel [mailto:karim.adel@gmail.com <javascript:;>] Sent: Thursday, November 08, 2012 5:23 PM To: NANOG list Subject: Whats so difficult about ISSU
Hello,
We've been hearing about ISSU for so many years and i didnt hear that any vendor was able to achieve it yet.
What is the technical reason behind that?
If i understand correctly, the way it will be done would be simply to have extra ASICs/HW to be able to build dual circuits accessing the same memory, and gracefully switch from one to another. Is that right?
Thanks, Kim