29 Sep
2023
29 Sep
'23
6:26 p.m.
On Sep 29, 2023, at 15:14, William Herrin <bill@herrin.us> wrote:
On Fri, Sep 29, 2023 at 3:11 PM Owen DeLong <owen@delong.com> wrote:
You continue to assume that there is a fast SRAM cache. I’m not sure that is true. I think that all of the FIB RAM on the line cards is fast SRAM and no cache.
Hi Owen,
I'm less assuming it and more reading it from this SIGCOMM paper: https://people.csail.mit.edu/ghobadi/papers/trio_sigcomm_2022.pdf
Fair enough, but interestingly, I think that the compiled line-card forwarding table probably always fits in the cache. Owen